FIELD OF THE INVENTION
The present invention relates to a batch erasable nonvolatile memory devices (hereinafter simply referred to as "flash memory"). a method of erasure therefor (eg., batch erasure) and an apparatus using same.
In a program operation in a flash memory with a power supply voltage Vcc of 5V, hot electrons which are produced near a drain are introduced into a floating gate to obtain a high-level state (logic 0) of a threshold voltage by setting a drain potential of a nonvolatile memory cell (hereinafter simply referred to as "memory cell") to approximately 4V and a potential of a word line to which a control gate is connected to approximately 11V. In an erase operations a tunnel current is generated by setting a source potential to approximately 4V and the word line to approximately -11V and the threshold voltage is set to a low-level state (logic "1") by ejecting a charge stored at the floating gate.
As shown in FIG. 14, in the initial state before aN erase operation, there are a group of memory cells for storing data having threshold voltages corresponding to logic "1" and a group of memory cells for storing data having threshold voltages corresponding to logic "0" and, after selecting the memory cells which have stored logic "1" data by carrying out read operation before erase operation and changing over data of all memory cells to the logic "0" state by carrying out pre-write and pre-verify operations for the memory cells which store "1" data, batch erase and erase verify operations are performed. At this time, some of data is depletively erased (deplete failure) due to variations of the effects resulting from variations of processes such as, for example, increase of a tunnel oxidized film and an impurity profile and internal parasitic resistance of internal potential and variations of a threshold voltage due to batch erases. If there is even one memory cell with such negative threshold voltage, a current flows into the memory cell and a read operation is disabled even though the word line to which this memory cell is connected is not selected. Therefore, various methods have been proposed to prevent the above-described deplete failure by detecting the depletively erased memory cell and rewriting the data. Such preventive measures against the deplete failure are disclosed in Japanese Patent Application Laid-Open Nos. 6698/1992, 222994/1992 and 89688/1993.